LCD Controller - TFT LCD Panels (AXI Bus). Resolutions 4096x4096 down to 320x200 @120 & 60 Hz; 1,2,4,8,16,18,24,32 bits/pixel

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Digital Blocks

IP Name

DB9000AXI TFT LCD Controller (LCDC)

Provider

Digital Blocks

Description

LCD Controller - TFT LCD Panels (AXI Bus). Resolutions 4096x4096 down to 320x200 @120 & 60 Hz; 1,2,4,8,16,18,24,32 bits/pixel

Category

IP Catalog : Digital Core IP : Controllers : LCD

Portability

ASIC, FPGA, Structured

Process Node

all

Type

Soft IP

Maturity

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Overview

The Digital Blocks DB9000AXI TFT LCD Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Interconnect to a TFT LCD panel. The DB9000AXI contains a selectable 256 / 128 / 64 / 32-bit AXI Master Interface that targets higher resolution, higher color depth TFT LCD panels, with their resulting high frame buffer memory data bandwidth requirements.
The DB9000AXI IP Core can be implemented in an ASIC, ASSP, or FPGA device with an embedded microprocessor, an AMBA AXI / AHB Interconnect fabric, and SDRAM Controller for access to frame buffer memory. Typically, the microprocessor is an ARC, ARM, Intel, MIPS, OpenSPARC, PowerPC, or Tensilica processor and frame buffer memory is off-chip DDR / DDR2 / DDR3 SDRAM.

Features

Wide range of programmable LCD Panel resolutions: Maximum programmable resolutions of 4096x4096

Example LCD Panel high resolutions: Digital Cinema Systems (DCI) 2048 x 1080 2K image, 4096 x 2160 4K image, & Cinema Scope HD 2560 x 1080, 4096x2560, 3840x2160, 2560x2048, 2048x2048, 2048x1536, 1920x1200, 1920x1080, 1680x1050, 1600x1200, 1600x900

Example LCD Panel medium / small resolutions: 640x480, 640x400, 640x240, 640x200, 480x800, 480x640, 480x272, 480x234, 240x400, 240x320, 240x240, 320x200, 320x240

Programmable 1 Port or 2 Port TFT LCD Panel interfaces

Interface for 1 Port TFT LCD Panel: 18-bit digital (6-bits/color) , 24-bit digital (8 bits/color) LVDS / CMOS

Interface for 2 Port LVDS TFT LCD Panel: Two 24-bit digital (8 bits/color) LVDS / CMOS ports

Programmable frame buffer bits-per-pixel (bpp) color depths: 1, 2, 4, 8 bpp mapped through Color Palette to 18-bit LCD pixel; 16, 18, bpp directly drive 18-bit LCD pixel; 24 bpp directly drive 24-bit LCD pixel

Color Palette RAM to reduce Frame Buffer memory storage requirements and AXI Bus bandwidth

Programmable Output format support: RGB 6:6:6 or 5:6:5 or 5:5:5 on 18-bit digital interface; RGB 8:8:8 on 24-bit digital interface

9 sources of internal interrupts with masking control

Deliverables

Verilog RTL Source

Comprehensive testbench suite with expected results

Synopsys Design Constraints

Technical Reference Manual

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace

Datasheet

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Bus Interface

Optional Bus Interfaces: AHB, AXI, AXI4, Coreconnect, Avalon, PCI. Please contact Digital Blocks for more information.

Protocols

AMBA 2.0 AHB
AMBA 3.0 AXI
AMBA 4.0 AHB
AMBA 4.0 AXI
CoreConnect
OCP

Gate Count

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QIP Rating

This IP is not yet QIP rated.

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