LDPLL40-15T 300 to 450 MHz Delay-Locked Loop

QualCore

LDPLL40-15T 300 to 450 MHz Delay-Locked Loop

• IP Catalog : Analog & Mixed Signal IP : Clock : DLL
• IP Catalog : Off-Chip Interface IP : Embedded I/O Cores : DLL

• Integrates a delay line, a phase detector, a low pass filter and all associated support circuitry
• Operates when the powerdown signal (PD) is a logic level 0, and goes into a powerdown state when the powerdown signal is a logic level 1