Includes all high-speed analog functions for a dual channel serializer and single channel deserializer and is optimized for low power operation at data rates from 584Mbit/s to 2.4Gbit/s. Alternative 10b and 40b input and output datapaths simplify design of link layers created from RTL using regular standard cells and regular synthesis, place and route flows. Excellent supply noise immunity in the CDR and TX PLLs makes the SerDes ideal for use in noisy mixed signal SoC environments.
Features
Data rates of 584bit/s to 2.4Gbit/s
Compatible with Gigabit Ethernet, SATA1, FibreChannel 1 & 2, and JESD 204A
Separate PLLs for Tx and Rx support a single reference clock or separate references from 20MHz to 400MHz
Separate Serializer and Deserializer macros simplify assembly of arbitrary single- or multi-lane configurations
40bit datapath for easy SP&R of link layer
Flexible driver and receiver circuits compatible with LVDS and CML standards with programmable low power settings
Compatible with multiple IO libraries
Trimmable on-die termination ensures excellent signal integrity
High-speed loop-back path simplifies production testing
Low power - SerDes only 6.1mW @ 584Mbit/s
Deliverables
GDSII & CDL Netlist (MG Calibre Compatible)
Comprehensive datasheet/application note (PDF)
Behavioral Verilog Model
Liberty timing models (.lib)
LEF
Market Category
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others