The BA317 is a high-performance, flexible DDR3/DDR2-SDRAM memory controller developed, validated and licensed by Barco Silex. It supports both Single Data Rate (SDR) and Double Data Rate (DDR/DDR2/DDR3) SDRAM devices.
The BA317 is an assembly of modules (controller core, user ports and physical interface). According to the user needs, a top-level can be automatically generated with all modules included.
The controller core includes a multi-port arbiter and a command sequencer. It is optimized to achieve high bandwidth by mixing accesses to the different banks of the SDRAM. It generates burst of 8 data with auto-precharge option, allowing continuous data transfer in case of long bursts.
The user port includes FIFO (for both data and addresses). Each port can have a different data bus width (larger or smaller than the SDRAM bus width). The user port provides access to individual data. It manages the generation of SDRAM burst.
The physical interface manages the double data rate and the source synchronous data sampling.
Supports SDR, DDR, DDR2 and DDR3 memory devices
Multi-port arbiter designed to achieve high bandwidth
Supports a wide variety of FPGA (Virtex-5, Virtex-6, Virtex-7, Artix-7, Kintex-7, Spartan-6, Stratix-III, Stratix-IV, Stratix-V, Arria-2, Arria-5, Cyclone III…)
Each port can have its own asynchronous clock and a specific data bus width
Support several user interfaces (AXI-4, Avalon-MM, buffered, unbuffered, ...)
Can be connected to PLB/OPB bus on Xilinx device (via IPIF interface)
Flexible DDR/DDR2/DDR3 PHY interface
Automatically generates the initialization sequence and periodic refresh
Netlist or RTL
Communications, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others