NIST FIPS-197 Compliant Ultra-Low Power AES IP Core

Estimate your chip with this semiconductor IP

Noesis Technologies

IP Name

ntAES8

Provider

Noesis Technologies

Description

NIST FIPS-197 Compliant Ultra-Low Power AES IP Core

Categories

IP Catalog : Digital Core IP : Security : Decryption

IP Catalog : Digital Core IP : Security : Encryption

Portability

ASIC, FPGA, Structured

Process Node

all

Type

Soft IP

Maturity

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Overview

ntAES8 core implements the NIST FIPS-197 Advanced Encryption Standard and can be programmed to either encrypt or decrypt 128-bit blocks of data using a 128-bit, 192-bit or 256-bit key.

The ntAES8 has been carefully designed to require minimum logic resources rendering it an ideal solution for low power applications. This has been
achieved by using an 8-bit data path size which means that 16 clock cycles are required to load/unload the 128-bit plaintext/ciphertext block.

The encryptor receives the 128-bit plaintext block in 8-bit input symbols and generates the corresponding 128-bit ciphertext block in 8-bit output symbols using a supplied 128, 192, or 256-bit AES key. The pre-computed key values
are read from an internal round key RAM. A key expander module is provided as an optional module to allow automatic generation and loading of the round key RAM. The decryptor implements the reverse function, generating plaintext from supplied ciphertext, using the same AES key as was used for encryption.

The implementation is very low on latency, high speed with a simple interface for easy integration in SoC applications.

Features

Compliant to Advanced Encryption Standard (AES) (FIPS PUB 197)

Supports both encryption and decryption functions

Supports 128/192/256-bit Cipher keys

Processes an 128-bit block in 480/582/684 clock cycles for 128/192/256-bits cipher keys respectively

Supports ECB, CBC, CFB, OFB and CTR modes

Optional Key Expansion module

Supports I/O data flow control capability

Exhibits highly optimized performance-silicon area ratio

Ideal for ultra-low power applications

Silicon proven in ASIC and FPGA technologies for a variety of applications

Deliverables

Fully commented synthesizable VHDL or Verilog source code or FPGA netlist

VHDL or Verilog test benches and example configuration files

C++ model

Comprehensive technical documentation

Technical support

Market Category

Communications

Datasheet

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Gate Count

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QIP Rating

This IP is not yet QIP rated.

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