OTP/eMTP: 256 Kbit NVM in 65nm Standard Logic CMOS process

Estimate your chip with this semiconductor IP

Sidense

IP Name

SiPROM_TSMC65GP25_2Kx128_4S4Y2_AF

Provider

Sidense

Description

OTP/eMTP: 256 Kbit NVM in 65nm Standard Logic CMOS process

Categories

IP Catalog : Digital Core IP : Memories : Non-volatile RAM

IP Catalog : Digital Core IP : Memories : EEPROM

IP Catalog : Digital Core IP : Memories : eFuse

Portability

ASIC, Structured

Process Node

65nm/TSMC/GP

Type

Hard IP

Maturity

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Overview

OTP (One-Time Programmable) or eMTP (Emulated Multiple-Time Programmable) memory IP available in a standard logic CMOS process requiring no additional masks or process steps. Replacement for eFuse, Flash and mask ROM. Non-volatile memory (NVM) IP is available in a wide range of configurations (8Kbits to several Mbits) for a broad range of analog and digital applications including encryption and security keys, IDs, code storage, digital rights management (including HDMI) and analog trimming.

Features

No Additional Masks or Process Steps

Very Secure & Reliable

Low voltage operation

Access times down to 10ns

Secure Program Lock Function

>20 years retention

Programmable on Tester, at Wafer probe, or in the Field

Low power

Very Small Area

Wide I/O width 8 to 128 bits

Deliverables

GDS Database

Verilog Models

.lib files

Full Data Sheet

Application Notes

Market Category

Automotive, Communications, Consumer Electronics, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Bus Interface

Serial/Parallel

Size

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"Aptina chose Sidense OTP for storing calibration and lens correction information in our image sensor and companion chip products for its small macro area, reliable field programmability to support correction in finished modules, and scalability to new process nodes for future product development. Because Sidense’s OTP does not add any additional processing steps or masks to our sensor process, Aptina benefits with a cost and time savings. "

Sion Quinlan, Director of Circuit IP
Aptina

View More Testimonials

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