PCI Verification IP in System Verilog (OVM/VMM) & Verilog

Estimate your chip with this semiconductor IP

nSys Design Systems

IP Name

PCI_nVS

Provider

nSys Design Systems

Description

PCI Verification IP in System Verilog (OVM/VMM) & Verilog

Type

Verification IP

Overview

The nVS for PCI is a comprehensive Verification IP solution for pre-silicon functional verification of PCI designs. The nVS allows design & verification engineers to quickly & extensively test the entire functionality of their PCI compliant designs.

Availability of Test Suites enables the designers to focus on features unique to their design. The nVS leverages advanced verification techniques in creating a versatile testbench environment.

Features

Compliant to PCI 2.3 specification

Supports 32/64 bit address data

Supports back to back cycles

Provides error injection with a wide variety of error types

Scalable architecture for use as a standalone test environment or embedding in an SoC environment

On-the-fly protocol and data checking

Support for multiple instantiations to create complex verification environment

Consistency of interface, installation, operation & documentation across nVS family

Generates all types of PCI transactions as a Master

Supports memoery modeling of all memory spaces (configuration/IO/Memory)

Deliverables

Validated PCI Verification Suite: BFM, Monitor, Checker

Test suites in source code

User manual and application notes

Market Category

Data Processing

Datasheet

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Bus Interface

PCI

QIP Rating

This IP is not yet QIP rated.

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