PCI Verification IP in System Verilog (OVM/VMM) & Verilog
The nVS for PCI is a comprehensive Verification IP solution for pre-silicon functional verification of PCI designs. The nVS allows design & verification engineers to quickly & extensively test the entire functionality of their PCI compliant designs.
Availability of Test Suites enables the designers to focus on features unique to their design. The nVS leverages advanced verification techniques in creating a versatile testbench environment.
Compliant to PCI 2.3 specification
Supports 32/64 bit address data
Supports back to back cycles
Provides error injection with a wide variety of error types
Scalable architecture for use as a standalone test environment or embedding in an SoC environment
On-the-fly protocol and data checking
Support for multiple instantiations to create complex verification environment
Consistency of interface, installation, operation & documentation across nVS family
Generates all types of PCI transactions as a Master
Supports memoery modeling of all memory spaces (configuration/IO/Memory)