The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable for PC and consumer electronics applications that require low EMI. It does not provide any deskew functionality. It contains a 1-64 divider at the reference clock input, a 1-256 or larger integer divider and a 1-256 or larger fractional divider in the internal feedback path, with as many as 4 bits of precise fractional-N control, and a 1-8 divider at the output. It can generate precise and adjustable frequency spreading depths (1.5% typical and up to around 10%) and rates (30KHz typical). The outputs are 50% duty cycle for all output divider values.
- Designed for PC, networking, and consumer-electronics applications where spread-spectrum clock sources are required to satisfy FCC requirements for peak RF spectral emissions.
- bandwidth, Spreading rate, and Spreading amount are Precisely adjustable to allow the designer to dial-in the desired characteristics.
- Feedback divider with 8 fractional bits allows the frequency to be set more precisely when the bandwidth is reduced.
- GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
"Our mission is to provide predictable, reliable and cost-effective ASIC solutions, while reducing risk at each step of the process and improving time-to-market. True Circuits PLLs and DLLs are feature rich, easily integrated and well supported, helping us to deliver quality analog IP and faster design implementations to our ASIC customers. "
Hans Bouwmeester, Director of IP Open-Silicon, Inc.