ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog
Visit IP Talks at DAC 2013 to learn the latest about semiconductor IP

Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com
Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com

Parallel ATA Host Controller

Estimate your chip with this semiconductor IP
Evatronix
Semiconductor IP Vendor InformationView all semiconductor IP from EvatronixContact Semiconductor IP VendorSemiconductor IP Customer Testimonials Add Semiconductor IP to an IP List

Share
Email Semiconductor IP Datasheet Print Semiconductor IP Datasheet   
IP Name
ATAIF Parallel ATA Host Controller
Provider

Evatronix

Description

Parallel ATA Host Controller

Category
Portability
ASIC, FPGA, Structured
Process Node
900nm/TSMC
Type
Soft IP
Maturity
Please login or register to view this data
Overview
The ATAIF implements a host controller for non-volatile memory devices using the parallel interface known
as ATA (Advanced Technology Attachment), IDE (Integrated Drive Electronics), and ATAPI (Advanced Technology Attachment Packet Interface).
The core provides a simple interface to memory devices such as hard-disk drives, CDROM/DVD players/writers, Compact Flash storage, and PC Card devices.
It supports PIO modes 0 to 4; Multi-word DMA modes 0, 1 and 2; Ultra ATA -33, -66, -100 and -133; and implements an interface to the IDE bus.

Features
  • Supports one or two IDE devices
  • Supports synchronous Ultra ATA-33, -66, -100, 133 and -167
  • Programmable I/O modes: 0, 1, 2, 3, 4, 5 and 6
  • Generic SFR interface with configurable data bus: min. 4-bit, no upper limit
  • Multi-word DMA modes 0 to 3
  • Configurable Internal FIFO address bus width: min. 4-bit, no upper limit
  • DMA Controller provides synchronous data transmission interface
  • Master FIFO Controller data transmission interface
  • Transmit/Receive buffers operate as internal configurable FIFOs
  • Available also with AMBA®AHB, OCP, AXI, PLB and Avalon interfaces
Deliverables
  • VHDL/Verilog source code
  • Synthesis support for Synopsys® and Cadence tools with a set of synthesis scrips
  • Simulation support (for Mentor Graphics® and Cadence®) with a set of scripts and macros
  • A collection of tests which are executed directly by the Test Bench
  • Additional documentation: Design Specification; Verification Specification and Test Plan; Integration Manual with User Guide
Market Category
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
Please login or register to view this data
Bus Interface
optional: AMBA®AHB or On-Chip Peripheral Bus interface or Avalon interface
Gate Count
Please login or register to view this data
QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"Fujitsu Telecommunications Europe was recently presented with a major product re-design issue that required a significant number of its design and development processes to be fast-tracked against a very aggressive timeframe. We engaged with Evatronix to assist us in this endeavour and were highly impressed with the responsiveness, quality of work and professionalism of the company. We would quite happily work with Evatronix in the future. "

Mark Hanvey, Director of Procurement
Fujitsu Telecommunications Europe Ltd

 
 
     Related IP from Evatronix you may be interested in...
IP Name Description
ATAIF SD Parallel ATA Disk Host Software Driver
NANDFLASH-CTRL_SD NAND Flash Memory Controller Software Driver
TV-OUT CTRL Video Display Controller Video Display Controller
DISPLAY-CTRL- High Resolution Display Controller Ultra High Resolution Display Controller
DISPLAY-CTRL-4K 4K Digital Cinema Display Controller for HDMI, DVI and DisplayPort transmitters
 
 
Search For Semiconductor Design and Verification IP
Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
IBM
SilTerra
SMIC
TSMC
Tower
UMC
X-FAB
advertisement
Category
Vendor
Portability
ASIC FPGA Structured
IP Quality
QIP Rated

     Language: Search for Semiconductor Design and Verification IP at ChipEstimate.com English | Search for Semiconductor Design and Verification IP at ChipEstimate.jp Japanese | Search for Semiconductor Design and Verification IP at ChipEstimate.cn Chinese
 
      ChipEstimate.com Chip Planning & IP Portal -- Copyright © 2013 ChipEstimate.com. All rights reserved.
ChipEstimate.com Twitter feed  ChipEstimate.com Semiconductor IP on LinkedIn  ChipEstimate.com Semiconductor IP Channel on YouTube  ChipEstimate.com Semiconductor IP on Facebook  ChipEstimate.com Semiconductor IP on Google+ 


       Feedback  Privacy Policy  Terms of Use  Newsletter & Tech Talk Archive  IP Catalog Site Map