Rambus® Gen2 PHY Cells Designed for PCI Express (PCIe 2.0)

Rambus

Rambus® Gen2 PHY Cells Designed for PCI Express (PCIe 2.0)

• IP Catalog : Analog & Mixed Signal IP : PHY
• IP Catalog : On-Chip Bus IP : PCI Express
• IP Catalog : On-Chip Bus IP : SATA

• Compliant to PCI Express Base specification 2.0 and 1.1 and SATA specificationsr2.5
• Flexible, configurable link design
• Feature-rich in-system diagnostics and testability
• nteroperable with industry-standard PCI Express digital controller; Rambus provides a seamlessly integrated PHY and digital controller
• PCI Express functions including Rx detect, Beacon transmitter and detection, Tx electrical idle and Rx idle detection, programmable serial Tx swing with de-emphasis equalization
• 100MHz, 125MHz, 250MHz reference clock frequencies
• Spread Spectrum Clocking support
• Robust test features, including AC and DC JTAB boundary scan, Serial and Parallel loopback, BIST and PRBS generation and checking, Scan, Rx jitter tolerance adjustment
• Architecture targeteable to 90 nm, 65 nm and 45 nm process geometries
• Comprehensive design integration support

• GDSII layout database
• Verilog model and testbench
• .lib Timing Model
• I/O HSPICE Models
• Documentation