A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error correction. It can be targeted for both ASIC and FPGA technologies. It uses a continuous, very high-speed, time-domain Reed-Solomon decoding algorithm and supports different Reed-Solomon coding standards.
Category
Portability
Process Node
Type
Maturity
Market Category
Bus Interface
QIP Rating
IP Catalog : Digital Core IP : Communications : Error Correction/Detection
IP Catalog : Digital Core IP : Mathematic Functions : Encoder/Decoder
IP Catalog : Digital Core IP : Communications : Wireless : 802.11
ASIC, FPGA, Structured
180nm
Soft IP
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Automotive Communications Consumer Electronics Data Processing Industrial and Medical Military/Civil Aerospace Others
custom
This IP is not yet QIP rated.

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