RSD1
RSD1
Overview:

A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error correction. It can be targeted for both ASIC and FPGA technologies. It uses a continuous, very high-speed, time-domain Reed-Solomon decoding algorithm and supports different Reed-Solomon coding standards.

Deliverables

Test Bench (Verilog Source Code)
Documentation
C Models
Free Tech Support

Features

Continuous, very high-speed, time-domain Reed-Solomon decoding algorithm
Supports different Reed-Solomon coding standards
Supports error and erasure decoding
Code rate can be dynamically varied
Parameterizable bits per symbol (M)
Programmable codeword length (NVAL) with parameterizable maximum value (N)
Programmable number of errors (TVAL) with parameterizable maximum value (T)
Shortened codes supported (NVAL,TVAL)
User configured primitive field and generator polynomial
Predictable decoder latency

Details

Category

Portability

Process Node

Type

Maturity

Market Category

Bus Interface

QIP Rating

IP Catalog : Digital Core IP : Communications : Error Correction/Detection
IP Catalog : Digital Core IP : Mathematic Functions : Encoder/Decoder
IP Catalog : Digital Core IP : Communications : Wireless : 802.11

ASIC, FPGA, Structured

180nm

Soft IP

Please login or register to view this data

Automotive Communications Consumer Electronics Data Processing Industrial and Medical Military/Civil Aerospace Others

custom

This IP is not yet QIP rated.

Vendor

ASICs World Services specialize in providing top-notch IP Cores and design services. We will as

CONTACT VENDOR

Find the component you need without hours of searching.

Testimonials

No testimonials yet

Whitepapers

The Case for Developing Custom Analog

The contents of this document are owned or controlled by S3 Group and are protected under applicab...

DOWNLOAD