Silterra 130nm G FSG Std-Vt ASAP-Logic High-Density Standard-Cell-Library

Estimate your chip with this semiconductor IP

Synopsys

IP Name

Logic Libraries, Std-Vt ASAP, High-Density, Silterra 130nm G

Provider

Synopsys

Description

Silterra 130nm G FSG Std-Vt ASAP-Logic High-Density Standard-Cell-Library

Category

IP Catalog : Digital Core IP : Standard Cell Libraries : Density Optimized

Portability

ASIC

Process Node

130nm/Silterra/G

Type

Hard IP

Maturity

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Overview

The DesignWare® ASAP™ Logic product line consists of metal programmable and standard cell libraries designed to meet the highest quality and performance standards for 180 nm to 90 nm process nodes. The DesignWare ASAP Logic cell libraries are production-proven in over 2500 designs. Many of those chips were produced for consumer applications in very high volumes. Each ASAP Logic architecture is developed to fit a particular target process and application segment. All cells come with hand optimized circuit design and layout for optimized performance, power consumption, and minimized raw cell area. The DesignWare ASAP Logic cell libraries are correlated to silicon for maximum accuracy and predictability of results. The DesignWare ASAP Logic product lines consist of Metal Programmable Cell Libraries and Standard Cell Libraries.

Features

Consists of metal programmable and standard cell libraries

Designed to meet the highest quality and performance standards

The DesignWare ASAP Logic cell libraries are production-proven in over 2500 designs

Developed to fit a particular target process and application segment

All cells come with hand optimized circuit design and layout for optimized performance, power consumption, and minimized raw cell area

ASAP Logic Cell libraries are correlated to silicon for maximum accuracy and predictability of results

Deliverables

.lib

LEF

GDS

Verilog

CDL and other industry standard design views

Market Category

Communications, Consumer Electronics, Data Processing, Military/Civil Aerospace, Others

Datasheet

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Size

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "

Laurent Sibony, Director of ASIC Designs
Sequans

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