Xtensa-7
Xtensa-7
Overview:

Tensilica's Xtensa 7 processor is a configurable, extensible and synthesizable 32-bit RISC processor core. The Xtensa 7 processor is extremely versatile - it is well suited for control-plane as well as data-plane SOC applications. By selecting and configuration predefined elements of the architecture and by inventing completely new instructions and hardware execution units, the Xtensa 7 processor can deliver performance levels orders of magnitude faster than standard 32-bit processor cores. Designers define new instructions, adding Verilog-like descriptions of datapaths, execution units, and register files that can deliver performance, area, and power characteristics equivalent to custom logic design. Or, the designer can use the XPRES Compiler to analyze the C/C++ algorithm and automatically suggest configuration options and extensions that will run that algorithm faster. Compared to traditional hardware design, Xtensa processors deliver similar quality of results with the added benefits of accelerated design time and post-silicon software programmability, making Xtensa 7 processors ideal choices for all complex SOC designs.

Deliverables

Full documentation
Eclipse-based tools

Features

Highly configurable architecture so designers can include only the required features, optimizing the processor for the smallest die size and lowest power
Before committing to silicon, system designers can explore multiple architectures by making area, speed, power and code-density design tradeoffs based on real-time feedback from the Xtensa Xplorer environment
Pre-verified, correct-by-construction RTL generation lowers verification efforts
32-bit synthesizable RISC architecture with 5-stage pipeline, 16/24-bit instruction encoding with modeless switching
XPRES Compiler automates generation of instruction extensions from C/C++ algorithms
Automated fine and coarse-grain clock gating for ultra-low power
Local memories can include parity or ECC
Reduces design risk with post-silicon programmability using processors instead of RTL blocks

Details

Category

Portability

Process Node

Type

Maturity

Market Category

Bus Interface

QIP Rating

IP Catalog : Digital Core IP : Processors : CISC
IP Catalog : Digital Core IP : Processors : RISC

ASIC, FPGA, Structured

90nm

Hard IP

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Automotive Communications Consumer Electronics Data Processing Industrial and Medical Military/Civil Aerospace Others

AMBA AHB, AXI, PIF

This IP is not yet QIP rated.

Vendor

Tensilica, Inc. is the recognized leader in configurable processor technology and has leveraged

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