Sub-frame latency JPEG 2000 encoder

Estimate your chip with this semiconductor IP

Barco Silex

IP Name

BA130 Sub-frame latency JPEG 2000 encoder

Provider

Barco Silex

Description

Sub-frame latency JPEG 2000 encoder

Categories

IP Catalog : Digital Core IP : Audio/Video : Image Coders/Decoders : JPEG

IP Catalog : Digital Core IP : Audio/Video : Video Coders/Decoders

Portability

ASIC, FPGA

Process Node

all

Type

Soft IP

Maturity

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Overview

Capitalizing on its long-term experience with JPEG 2000 hardware coding, Barco Silex offers a large JPEG 2000 portfolio including this compact real-time hardware encoder engine that is optimized for low latency video applications.

The core architecture offers a flexible and high-speed solution to meet the challenges of high-end broadcast performance requirements, sustaining up to 180 frames per second in 1080i format, for compressed stream bitrates extending up to 400 megabit per second.

The BA130 IP core encodes YUV 4:2:2 frames up to 1080p or larger and generates compressed stream which are compliant with the ISO/IEC 15444-1 specifications (JPEG 2000). This IP is the complement of the BA129 low-latency JPEG2000 decoder IP, to which it can be directly connected.

The core performs the following video compression operations of the normalized encoding process: discrete wavelet transform (DWT), quantization, entropy encoding, rate allocation and stream packetizing. It accepts pixels on its input interface with up to 12 bits per color components and it generates a JPEG 2000 stream at its output interface. Optional modules allow for video interfacing, and temporary output stream buffering facilitating integration in the user application.

The BA130 IP provides a single-chip FPGA solution for 720p30-180, 1080i30-180 and 1080p30-90 video modes, with a total pixel-to-pixel latency below 10ms for 1080i/p60, below 5ms for 1080i/p120 and below 3ms for 1080i/p180 when used together with the BA130 encoder.

The flexible FPGA architecture allows the user to build a secure encoder by integrating Barco Silex cryptography IP cores.

Features

Sub-frame latency encoding (< 5ms)

Full image encoding (no tiling)

Compliant with JPEG 2000 (ISO/IEC 15444-1)

Integrated Intellectual Property (IP) core for JPEG 2000

Customizable output bit rate up to 200Mbps / 400Mbps

Flexible Tier-2 for rate allocation

Single-chip FPGA solution

Minimal user intervention

Fully synchronous design

Deliverables

RTL Code or netlist

Functional simulation testbench

Synthesis script

Full documentation

Market Category

Communications, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Gate Count

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QIP Rating

This IP is not yet QIP rated.

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	IP Name			Description
	BA115JPEGCD			Fast JPEG color decoder
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	BA110 HD/DCI JPEG 2000 Encoder			Multi-channel HD/DCI JPEG 2000 encoder
	BA109 HD/DCI JPEG 2000 Decoder			Multi-channel HD/DCI JPEG 2000 decoder
	BA129 Sub-frame latency JPEG 2000 decoder			Sub-frame latency JPEG 2000 decoder