TSMC 40nm LP LowK SiWare-Logic High-Speed Multi-Channel-Standard-Cell-Library

Estimate your chip with this semiconductor IP

Synopsys

IP Name

Logic Libraries, LowK SiWare, High-Speed, Multi-Channel, TSMC 40nm LP

Provider

Synopsys

Description

TSMC 40nm LP LowK SiWare-Logic High-Speed Multi-Channel-Standard-Cell-Library

Category

IP Catalog : Digital Core IP : Standard Cell Libraries : Density Optimized

Portability

ASIC

Process Node

40nm/TSMC/LP

Type

Hard IP

Maturity

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Overview

The SiWare™ Logic Libraries product line includes yield-optimized, design for manufacturability (DFM) compliant standard cells for a wide variety of design applications at the advanced nodes. The SiWare Logic Libraries are offered using three separate architectures - High-Density (HD), Ultra-High-Density(UHD) or High-Speed(HS) - to optimize circuits for area, speed, and power trade-offs. Ideal for customers in the graphics, networking, storage, cell phone and other high-performance applications requiring high density and low power, the 65 nm, 40 nm and 28 nm technologies provides a dashboard of options to enable reduced die size, optimal power management, high performance and test and repair options. This capability enables customers to differentiate their products with respect to speed, area, dynamic power, standby power and cost.

Features

Performance vs. Area: Select between High-Density vs. High-Speed SRAM compilers for 30-70% performance improvement

Performance vs. Leakage power: Power Saver mode saves 60% of static power as compared to Performance mode

Area vs. Dynamic power: Multiple bank options in SRAM compilers to tradeoff area for up to 55% lower dynamic power

Performance vs. Dynamic power: DVFS supported by ultra low voltage operation characterization at 20% below nominal voltage for 40% dynamic power reduction

Performance vs. Yield: Read/Write Margin settings and Sigma-based design characterization to manage local process variance based on memory size and number of memories per chip

Area vs. Yield: SRAM compilers have option to use column redundancy to tradeoff area for yield. Customers have reported 50%-250% better yield due to repairable memories

Testability Choices: Options for external, integrated at-speed test and redundancy

Supported by STAR Memory System

Deliverables

.lib

LEF

GDS

Verilog

CDL and other industry standard design views

Market Category

Communications, Consumer Electronics, Data Processing, Military/Civil Aerospace, Others

Datasheet

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Size

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "

Laurent Sibony, Director of ASIC Designs
Sequans

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