Although the Diamond 106Micro is extremely small, it employs a 5-stage pipeline so it can easily achieve 250 MHz in 130G process and up to 400 MHz in 90G process technology. By modelessly switching between 24- and 16-bit narrow instructions, it achieves a much higher code density than other 32/16-bit architectures. The local, tightly-coupled instruction and data memory on the Diamond Standard 106Micro can be used to store performance-sensitive code and data, for example, to achieve high performance on interrupt handlers.
The Diamond 106Micro has an iterative, multi-cycle (non-pipelined) 32x32 multiplier that greatly enhances performance on arithmetic and DSP code. The processor uses a non-windowed 16-entry AR register file to keep area low and that potentially does better on applications that have very deeply nested function calls, since it never throws an exception. The Diamond Standard 106Micro has a rich interrupt architecture with an integrated interrupt controller with 15 interrupts, and an integrated timer. This simplifies system design since no external hardware needs to be added for these functions.
Cache-less processor with memory protection unit
Dhryston MIPS: 1.22 DMIPS/MHz
Integrated interrupt controller with 15 interrupts at 2 priority levels
On-chip debugging hardware
Embedded trace support
AHB-lite and AXI bridges
Achieves high frequency: 400 MHz in 90G
Separate instruction and data memory interfaces
Comprehensive software tool set
Communications, Consumer Electronics, Data Processing, Industrial and Medical
"Tensilicas HiFi 2 audio DSP architecture is a widely adopted, advanced DSP core with over 30 voice and audio encoder and decoder software packages readily available. After a thorough technical evaluation of Tensilicas HiFi offering, we found that the Diamond 330HiFi was the right audio DSP for Samsung and will be a key DSP in our IP portfolio for years to come. "
G. S. Han, Vice President of Samsung Electronics System LSI Division