A semiconductor IP core that implements an extremely small 8-bit microcontroller executing the ASM51 instruction set. It includes peripherals for serial communication, a timer, a multi-purpose I/O port, hardware interrupts, and a JTAG debugger interface.
This 8051 core is based on the fast, configurable CAST R8051XC core (proven in hundreds of successful designs). Sample implementation results show it to require as little as 2,000 ASIC gates for 0.35 um (for the CPU). It achieves this low gate count by sharing resources between several stages of instruction set execution, with careful tuning of instruction cycle latency to reduce hardware resources.
Performance remains high: 4.1 times better than the original Intel™ 8051 as measured by Dhrystone MIPs per MHz. Communication with both built-in and external memories has been accelerated by de-multiplexing the address and data buses, while alternate port functions such as external interrupts and serial interface are available on separate pins.
The T8051 is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward. A complete On-Chip Debug Support (OCDS) debugging system compatible with the industry-standard Keil™ µVision Cx51 Development Tools IDE is also available.
100% MCS51® compliant Central Processing Unit ;Extremely small gate count, e.g., TSMC .18 ASIC process:CPU only = 2.8K ,CPU + peripherals = 5.2K (fits in 0.0539 mm2 footprint),Total, with OCDS debug = 8.5K ;
Dummy peripheral replacements for even lower gate count ; Low power consumption ; Fast: performance is 4.1 times classic 8051 (Dhrystone MIPS benchmarks; data available).
Input/Output port ;Single 8-bit I/O port ; Alternate port functions such as external interrupts and serial interface are separated, providing extra port pins when compared with the standard 8051
Interrupt Controller : Four Priority Levels with eleven interrupt sources (80C517-like) ; Eight External Interrupts -Two Low-Level or Falling-Edge Sensitive , Two Falling-Edge or Rising-Edge Sensitive , Four Rising-Edge Sensitive
Internal Data Memory interface -addresses up to 256 B of Data Memory Space ;
External Memory interface - addresses up to 64 kB of External Program Memory , addresses up to 64 kB of External Data Memory , De-multiplexed Address/Data Bus to ease the connection with memories , Program memory write mode
On-Chip Special Function Registers interface
Power Management Unit
On Chip Debug Support (OCDS)
HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
Reference design for proprietary development board, This design uses the T8051 and illustrates how to build and connect memories and port modules
Sophisticated HDL Testbench including external FIFOs, buffers, models of interfaces, and the core
Simulation script, vectors, expected results, and comparison utility; Synthesis (soft) or place and route (firm) script
Comprehensive user documentation, including detailed specifications and a system integration guide
"iSine provides custom ASIC and SoC solutions to multiple market segments (see www.isine.com). The quality and support of CAST IP cores have saved us valuable time to market with these products. In this highly competitive environment, this advantage is critical to the success of our company. CAST has repeatedly and quickly helped us out of last-minute jams and multi-vendor IP interface issues.