The USBHSIC-PHY is a complete mixed-signal transceiver macro-cell that implements the USB 2.0 High Speed Inter Chip (HSIC) layer for USB 2.0 High Speed Device and Host applications.
The USBHSIC-PHY consists of a logic macro, which is available as either hard or soft IP, and a hard-IP block that contains the special driver circuit that is mandated by the HSIC specification.
The HSIC standard exists because there are many applications where it makes sense to embed a subsystem that uses USB 2.0 within embedded applications that do not need to be connected to external devices.
The USBHSIC-PHY can be used for subsystems within a smartphone. The big advantage over conventional USB2 is the elimination of most of the power consumption and most of the chip area that would be required for conventional USB2 PHYs.
"Fujitsu Telecommunications Europe was recently presented with a major product re-design issue that required a significant number of its design and development processes to be fast-tracked against a very aggressive timeframe. We engaged with Evatronix to assist us in this endeavour and were highly impressed with the responsiveness, quality of work and professionalism of the company. We would quite happily work with Evatronix in the future. "
Mark Hanvey, Director of Procurement Fujitsu Telecommunications Europe Ltd