MUSBHPHY from is a high-speed USB 2.0 transceiver for use with host, embedded host, On-The-Go (OTG), and function controllers. Compliant with the UTMI+ level 3 (USB 2.0 Transceiver Macrocell Interface Plus) specification, the MUSBHPHY integrates high-speed, mixed-signal circuits to support High-Speed traffic at 480Mbps and is backward compatible to Full-Speed (12Mbps) and Low-Speed (1.5Mbps) data rates.
This transceiver is optimized for low power consumption, minimal die area (sub-1mm2), and high-data throughput. The MUSBHPHY comprises a complete on-chip physical transceiver solution with Electro Static Discharge (ESD) protection, full support for OTG and host functionality, and includes an optional charge pump to provide a 5V power supply to external USB peripherals.
The MUSBHPHYincludes a clock generation block with a PLL unit to ensure accurate high-speed data transmission from and to the transceiver. The MUSBHPHY requires a 12MHz reference clock input to the PLL unit.
The transceiver is available for the SMIC 130 nm standard digital process.
Fully compliant with USB 1.1 and 2.0
Supports High-Speed (480Mbps), Full-Speed (12Mbps), and Low-Speed (1.5Mbps)
Supports peripheral, host, embedded host, OTG, and hub applications
Dual 3.3V/1.2V supply
Rail-to-rail common mode differential receiver
Digital I/O for Tx & Rx USB OTG cable type
40um staggered bond pitch
Optional charge pump 100mA supply current at 4.4V Vbus under typical conditions
No external 5V supply needed
Scan-based DFT and loop back
GDSII layout & layer map
Place-and-route views (.lib, .lef)
LVS & DRC verification reports
Verilog Sim Model (NC-Verilog), Gate-level netlist & SDF timing
Test guidelines, layout guidelines, and application notes