USB3_DEV

Estimate your chip with this semiconductor IP

ASICS World Services

IP Name

USB 3.0 Device IP Core

Provider

ASICS World Services

Description

USB3_DEV

Categories

IP Catalog : On-Chip Bus IP : USB

IP Catalog : Digital Core IP : Communications : Receiver & Transmitter

Portability

ASIC, FPGA, Structured

Process Node

250nm

Type

Soft IP

Maturity

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Overview

A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of a USB Device interface.

Features

USB 3.0 SuperSpeed support, 5Gbit/s

USB 3.0 PIPE interface

Integrated DMA engine

Up to 16 fully configurable endpoints

Bulk, control, interrupt and isochronous endpoints and transfers

Full duplex operation support

Power Management support

Deliverables

Verilog source code or netlist

Test Bench (Verilog Source Code)

Documentation

Reference design incl. C code

Free Tech Support

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Bus Interface

WISHBONE, AHB, OPB, PLB, OCP and AVALON

Gate Count

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QIP Rating

This IP is not yet QIP rated.

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