Ultra High Resolution Display Controller

Estimate your chip with this semiconductor IP

Evatronix

IP Name

DISPLAY-CTRL- High Resolution Display Controller

Provider

Evatronix

Description

Ultra High Resolution Display Controller

Category

IP Catalog : Digital Core IP : Audio/Video : Other

Portability

ASIC, FPGA, Structured

Process Node

all

Type

Soft IP

Maturity

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Overview

The DISPLAY-CTRL is a synthesizable core intended
for use with Video DACs with RGB interface up to 24 bits per pixel, Horizontal and Vertical synchronization signals, and Blanking (Data Enable) signal.
The controller accepts two different input color formats: RGB 24 bits per pixel and RGB 15 bits per pixel. All horizontal and vertical timing parameters such as horizontal/vertical front porch, back porch and sync intervals are programmable.
In order to facilitate the use of the DISPLAY-CTRL core in AMBA bus-based microprocessor systems, an AHB Master 64-bit interface and AHB Slave 32-bit interface and FIFO controller are provided.
Examples of supported resolutions:
QVGA – 320 x 240 85Hz
VGA – 640 x 480 85Hz
SVGA – 800 x 600 85Hz
XGA – 1024 x 768 85Hz
SXGA – 1280 x 1024 85Hz
HD 720 – 1280 x 720 60Hz
UXGA – 1600 x 1200 60Hz
WSXGA+ – 1680 x 1050 60Hz
HD 1080 – 1920 x 1080 60Hz
WUXGA – 1920 x 1200 60Hz

Features

Input data formats: RGB24 (8:8:8) RGB15 (5:5:5)

Output interface for Video DAC: RGB24 (8:8:8) HSYNC and VSYNC signals or one composite Blanking (Data Enable) signal

Progressive scanning mode support

Fully configurable monitor frequencies and aspect ratios

Display functions with hardware support: Scrolling in horizontal and vertical directions Horizontal flip screen Sub-screen display

Dedicated unidirectional DMA controller with burst transaction support, configurable internal FIFO

Internal, event stimulated, interrupt request generation with masking capability,integrated test mode – generates color bar without any AHB bus transactions

Integrated with AMBA® bus: AMBA®AHB master unit to interface with the 64-bit data host memory, AMBA®AHB slave unit to interface with the 32-bit data host controller

Little-endian architectures supported

Deliverables

Verilog RTLsource code

Synthesis support for Synopsys® tools with a set of synthesis scripts

Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros

Extensive Verilog 2001 test bench, Documentation

30 days of technical support, 90 days of warranty against defects

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Bus Interface

AMBA AHB

Gate Count

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QIP Rating

This IP is QIP rated.

Customer Testimonial

"Fujitsu Telecommunications Europe was recently presented with a major product re-design issue that required a significant number of its design and development processes to be fast-tracked against a very aggressive timeframe. We engaged with Evatronix to assist us in this endeavour and were highly impressed with the responsiveness, quality of work and professionalism of the company. We would quite happily work with Evatronix in the future. "

Mark Hanvey, Director of Procurement
Fujitsu Telecommunications Europe Ltd

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