VeriSilicon CHRT 0.13μm 1.2V/2.5V DUPIO_01 Library

Estimate your chip with this semiconductor IP

VeriSilicon

IP Name

C13V25_DUPIO_01

Provider

VeriSilicon

Description

VeriSilicon CHRT 0.13μm 1.2V/2.5V DUPIO_01 Library

Category

IP Catalog : Off-Chip Interface IP : I/O Libraries : General Purpose I/O

Portability

ASIC

Process Node

130nm/GLOBALFOUNDRIES

Type

Hard IP

Maturity

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Overview

VeriSilicon CHRT 0.13?m 1.2V/2.5V DUP I/O Cell Library developed by VeriSilicon is optimized for Chartered Semiconductor Manufacturing (CHRT) 0.13?m Logic 1P8M Salicide 1.2/2.5V process. This library supports Device Under Pad (DUP). This library includes analog I/O cell part and digital I/O cell part, and the digital I/O cells can take 3.3V tolerance and work with configurable and variable driving strength between 2mA - 24mA. This library supports Inline I/O pad.

Features

CHRT 0.13um Logic 1P8M Salicide 1.2V/2.5V process

Low area and low cost design using DUP technique

1.2V core power, 2.5V IO, digital IO supports 3.3V tolerance

This library includes analog I/O cell part

Configurable output driving capability with different slew rate

Supports configurable pull up and pull down resistor

Supports both CMOS input and Schmitt input with LVTTL compatible

Provides 2Mhz ~ 27Mhz OSC IO cell

Suitable for six, seven, or eight metal layers of physical design

Competitive pad pitch and height

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Size

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QIP Rating

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