The MAC-1G Ethernet controller is a synthesizable HDL core of a high-speed LAN controller. It implements Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for media
access control over the 10Mbps, 100Mbps and 1Gbps
Ethernet.
Features
IEEE 802.3 CSMA/CD standard compliance enables 10/100/1000 Mbps Ethernet modes
Support for half- and full-duplex Ethernet links
Compatible with a wide range of PHY interfaces - MII, GMII, RMII, RGMII
Internal OCP socket with AMBA®AHB and generic PVCI wrappers for system bus interface
Advanced mechanism for flexible address filtering against physical addresses and/or hash table
Scatter-gather DMA controller with a configurable 8/16/32/64- bit data bus length
Descriptor/buffer architecture for data storage
Configurable transmit/receive FIFOs with programmable threshold levels and
Fully-automated MII Serial Management data framing for integration with an external PHY
Low power capabilities
Deliverables
VHDL/Verilog source code
Synthesis support for Synopsys® and Cadence® tools with a set of synthesis scripts
Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros
Extensive HDL Test Bench
Complete documentation
Market Category
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
"Fujitsu Telecommunications Europe was recently presented with a major product re-design issue that required a significant number of its design and development processes to be fast-tracked against a very aggressive timeframe. We engaged with Evatronix to assist us in this endeavour and were highly impressed with the responsiveness, quality of work and professionalism of the company. We would quite happily work with Evatronix in the future. "
Mark Hanvey, Director of Procurement Fujitsu Telecommunications Europe Ltd