The MAC-1G-L implements a lean, gigabit-speed LAN controller using the Carrier Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by the IEEE 802.3 standard for media access control over Ethernet. The core uses a standard Gigabit Media Independent Interface (GMII). It provides full-duplex operation for 10/100/1000 Mbit/s transmission modes and, if desired, half-duplex operation for 10/100 Mbit/s modes. Configurable features allow tailoring the data interface bus width (8-, 16-,32 or 64-bit) as well as the transmit and receive FIFO sizes (64B to 64kB). The MAC-1G-L is designed for easy reuse in ASICs and FPGAs. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset. Therefore scan insertion is straightforward.
Features
Network interface features
Data link layer functionality
Flexible address filtering
Transmit/Receive dual port RAM interfaces:
Operate as internal configurable FIFOs
Programmable threshold levels
„Store and forward
Optional flow control functionality
Optional statistical counters
Deliverables
VHDL or Verilog source code for the MAC-1G-L
Synthesis support (Synopsys® and Cadence®) with a complete set of synthesis scripts
Simulation support (Mentor Graphics®, Cadence®) set of scripts and macros
Example chip of MAC-1G-L
Complete documentation, Design support including consulting
Market Category
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
"Fujitsu Telecommunications Europe was recently presented with a major product re-design issue that required a significant number of its design and development processes to be fast-tracked against a very aggressive timeframe. We engaged with Evatronix to assist us in this endeavour and were highly impressed with the responsiveness, quality of work and professionalism of the company. We would quite happily work with Evatronix in the future. "
Mark Hanvey, Director of Procurement Fujitsu Telecommunications Europe Ltd