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ATAIF Parallel ATA Host Controller

ATAIF Parallel ATA Host Controller

Overview:

The ATAIF implements a host controller for non-volatile memory devices using the parallel interface known
as ATA (Advanced Technology Attachment), IDE (Integrated Drive Electronics), and ATAPI (Advanced Technology Attachment Packet Interface).
The core provides a simple interface to memory devices such as hard-disk drives, CDROM/DVD players/writers, Compact Flash storage, and PC Card devices.
It supports PIO modes 0 to 4; Multi-word DMA modes 0, 1 and 2; Ultra ATA -33, -66, -100 and -133; and implements an interface to the IDE bus.

Deliverables

Synthesis support for Synopsys® and Cadence tools with a set of synthesis scrips

Simulation support (for Mentor Graphics® and Cadence®) with a set of scripts and macros

A collection of tests which are executed directly by the Test Bench

Additional documentation: Design Specification; Verification Specification and Test Plan; Integration Manual with User Guide

Features

Supports one or two IDE devices

Supports synchronous Ultra ATA-33, -66, -100, 133 and -167

Programmable I/O modes: 0, 1, 2, 3, 4, 5 and 6

Generic SFR interface with configurable data bus: min. 4-bit, no upper limit

Multi-word DMA modes 0 to 3

Configurable Internal FIFO address bus width: min. 4-bit, no upper limit

DMA Controller provides synchronous data transmission interface

Master FIFO Controller data transmission interface

Transmit/Receive buffers operate as internal configurable FIFOs

Available also with AMBA®AHB, OCP, AXI, PLB and Avalon interfaces

Details

Category

Portability

Process Node

Type

Maturity

Market Category

Bus Interface

QIP Rating

IP Catalog : Digital Core IP : Memories : Flash

ASIC, FPGA, Structured

900nm/TSMC

Soft IP

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Communications Consumer Electronics Data Processing Industrial and Medical Military/Civil Aerospace Others

optional: AMBA®AHB or On-Chip Peripheral Bus interface or Avalon interface

This IP is not yet QIP rated.

Vendor

Evatronix develops digital and mixed-signal Intellectual Property (IP) cores with complementary

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