Single port AHB SRAM NOR Flash controller

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Barco Silex

IP Name

BA313P Static Memory-NOR Flash Controller

Provider

Barco Silex

Description

Single port AHB SRAM NOR Flash controller

Category

IP Catalog : Digital Core IP : Controllers : Memory

Portability

ASIC, FPGA

Process Node

all

Type

Soft IP

Maturity

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Overview

The BA313P is a AHB slave controller which provides interface to asynchronous external memory devices. It generates the control and address buses, and handles data bus buffering.

As an External Peripheral Interface, the BA313P I/O channels can be configured in Motorola 68- or Intel 80-style protocols. In each configuration, there are several options like multiplexing (using the ALE signal to send the address and data) and CS polarity.

As a NOR Flash controller, the BA313P generates Ready/Not Busy signals (XReady). The XReady input is resynchronized inside the BA313P. The XReady value is always observable through APB interface (XReady bit of SMCSTATUS register). Besides that, it is possible to trigger an interrupt on rising XReady edge. The interrupt must be enabled (RdyIntEn bit of SMCCONFIG register). When the interrupt occures, the corresponding status bit is set (RdyIntStat bit of SMCSTATUS register). This bit (and the interrupt) can be cleared by writing a zero.

In the case of the same set of external pins is shared with another memory controller (NandFlash Memory Controller for instance), the BA313P is able to interface with an EBI (External Bus Interface).

Features

NOR Flash controller with up to 10 chip select lines, max. 16 MByte of address space for each device

Individual 8, 16 or 32 bits data bus configuration for each line. Access to separate byte is possible in 16-bit mode, and access to separate byte or half-word in 32-bit mode

Individual wait state configuration, from 0 to 31 cycles

Little endian architecture

Byte lane control

Programmable output enable and write enable delays

Programmable bus turnaround

Write protection

Access type configuration : cs, ncs, or ncs & E

Non multiplexed and multiplexed data bus

Deliverables

Compiled model available on request for evaluation

Verilog RTL sources

Testbench

Documentation

Market Category

Others

Datasheet

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Bus Interface

AHB

Gate Count

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QIP Rating

This IP is not yet QIP rated.

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