Capitalizing on its long-term experience with JPEG 2000 hardware coding, Barco Silex's JPEG 2000 portfolio includes this compact real-time hardware decoder engine that is optimized for Digital Cinema and High-Definition video applications.
The core architecture offers a flexible and high-speed solution to the performance challenges of digital cinema, broadcast and post-production applications. It is able to sustain the high decoding requirements of the large DCI frame formats, including 4096x2160 (4K) resolution and frame rates up to 48 frames per second.
The BA109 IP core is a JPEG 2000 hardware decoder dedicated to DCI (Digital Cinema Initiatives) and HD video applications. It decodes streams compliant with the ISO/IEC 15444-1 specification (JPEG 2000). It is compliant with the DCI recommendation for video coding. It applies JPEG 2000 decoding on un-tiled large color frames with 4:4:4 or 4:2:2 color sub-sampling.
The core performs the complete video decompression operations of the normalized decoding process: stream parsing and header decoding, entropy decoding, inverse quantization, inverse discrete wavelet transform (IDWT) and inverse color transform (ICT/RCT). It supports a JPEG 2000 j2c file at its input interface and generates decoded samples at its output interface under the following formats: 4:4:4 or 4:2:2 color sub-sampling with 12-bit per color component.
Its flexible architecture and interfaces can easily be integrated in many environments.
The support for multi-channel is very well suited to stereographic 3D applications.
The IP core is optimized for speed and is able to deal with the demanding DCI and HD processing speeds: it is able to provide a single-chip FPGA solution for all 2K@24fps, 2K@48fps, 2K@60fps, 2K3D@24fps; 2K3D@30fps, 2K3D@60fps, 4K@24fps, 4K3D@24fps, 720p30/60, 1080i and 1080p30/60 image format. The flexible FPGA architecture allows the user to build a secure decoder by integrating Barco Silex cryptography decoders.
Multi-channel HD / DCI
Compliant with DCI (Digital Cinema Initiatives) recommendation
Compliant with JPEG 2000 (ISO/IEC 15444-1)
Integrated Intellectual Property (IP) core offering a full FPGA solution for HD and DCI JPEG 2000
Customizable input bit rate up to 250 Mbps / 500 Mbps / 1+ Gbps / lossless
XYZ, RGB, YUV (4:4:4, 4:2:2 or 4:2:0) color spaces with support for ICT/RCT color transform@
Single-chip FPGA solution for multi-channel
Fully autonomous decoder with automatic parameter extraction, minimal user intervention
Can be used for FPGA, ASIC and Structured ASIC technologies
Fully synchronous design
RTL code or netlist (depending on license type)
Functional simulation testbench
Data Processing, Industrial and Medical, Military/Civil Aerospace, Others