This deinterlacer IP core converts a standard interlaced video stream to progressive video format for further processing or display. Extremely efficient, the deinterlacer core requires little area and transforms the video with practically no delay.
The core implements the most popular basic deinterlacing algorithm, Bob with scan line interpolation. It accepts an industry-standard ITU-R BT.656 interlaced video stream (8-bit 4:2:2 video data mixed with audio, control, and other signals) which may optionally include user-defined SAV codes.
The BT.656 input video is typically 480i/576i, but higher resolutions are possible (requiring higher clock frequencies). The output video contains twice the pixels and has a frame rating matching the input's field rate. Additionally, the user can constrain the possible maximum horizontal resolution with a pre-synthesis parameter.
The deinterlacer core's synchronous control interface allows for easy integration with the system CPU via the address and data buses. The core's efficiency and small size contribute to significant power savings compared to more complex deinterlacers.
Developed for easy reuse in FPGA or ASIC applications, the core is available optimized for several technologies, with competitive utilization and performance characteristics.
Accepts an 8-bit, 4:2:2, YCrCr, video data stream in ITU Recommendation BT.656 video format
Supports NTSC, PAL, 1080i and all lower resolutions transmitted in conformance with the BT.656 format
Sophisticated BT.656 analyzer splits contents of the incoming video stream
Works with optional user-defined SAV (Start of Active Video) codes in the incoming video stream
Output frame rate equals the input field rate
Maximum horizontal resolution can be set as a pre-synthesis parameter to reduce logic resources
Includes write-through mode
Produces raster scan format of output video data
Minimum system clock speed equals two times the raw pixel clock speed
Fully synchronous design: all inputs and outputs are based on the rising edge of clock Includes complete documentation and testbench
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