Viterbi Decoder for DVB-T/H receivers

Estimate your chip with this semiconductor IP

NTLab

IP Name

Viterbi decoder

Provider

NTLab

Description

Viterbi Decoder for DVB-T/H receivers

Categories

IP Catalog : Digital Core IP : Communications : Error Correction/Detection

IP Catalog : Digital Core IP : Communications : Wireless : Digital Video Broadcast

Portability

ASIC, FPGA, Structured

Process Node

all

Type

Soft IP

Maturity

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Overview

This high performance Viterbi Decoder IP Core is intended for use as a constituent part of DVB-T/H receivers and can be targeted in any ASIC or FPGA technologies. The Decoder is used for decoding convolutionally encoded data with generator polynomials G0=133 and G1=171 and constrained length 7.

Features

High throughput (one result per clock)

Fully synchronous design using a single clock

Constraint length k=7, generator polynomials (G0, G1) = (171, 133)

ETSI 300 744 compliant

Decoder rate 1/2 (2/3, 3/4, 5/6, 7/8 at depuncturer use (optional))

1-bit hard decision or n-bits soft decision

Erroneous bits counter (optional)

Multipliers absence

4 RAMs with data bus width 64 and address bus width 6

Traceback length 192

Deliverables

Branch Metric Unit

Path Metric Unit

Traceback Unit

Depuncturer (ETSI 300 744 (1.5.1) compliant) (optional)

BER monitor (optional)

Market Category

Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Gate Count

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QIP Rating

This IP is not yet QIP rated.

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