Tiempo clockless crypto-processor core - TDES - is able to execute the standard ciphering and deciphering algorithms DES, DES-1, 3DES and 3DES-1. This IP is designed in Tiempo fully asynchronous and delay insensitive technology that allows ultra-low power consumption, ultra-low noise, ultra-low EMI, as well as robustness against attacks by power analysis & fault injections.
Primary targeted applications are chips for smart cards (with or without contact), RFID tags, sensor networks, systems embedding NFC technology and other secured applications.
Executes standard ciphering and deciphering algorithms DES, DES-1, 3DES and 3DES-1
Fully asynchronous (no clock) and delay insensitive (correctness of ciphering/deciphering is guaranteed regardless of any actual delay in internal gates and wires)
Ultra low power consumption: low energy, low current peaks
Ultra low electromagnetic emission (EMI/EMC)
High speed (independent from any system clock)
High robustness against any PVT (process, voltage, temperature) variation
High robustness against attacks by power analysis and fault injections (for secured applications)
Available as Verilog netlist ready for P&R (silicon-proven netlist)
As an option: Verilog netlist secured against attacks by power analysis and fault injection (with different levels of protection)
As an option: Verilog netlist strengthened for ultra low noise, ultra low EMI
Contact Tiempo for available technologies and libraries
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others