12-Bit 300MS/s Triple DAC in TSMC 55/65nm

Estimate your chip with this semiconductor IP

S3 Group

IP Name

DAC-S3TD300M12BT65GPA

Provider

S3 Group

Description

12-Bit 300MS/s Triple DAC in TSMC 55/65nm

Category

IP Catalog : Analog & Mixed Signal IP : D2A Converter

Portability

ASIC

Process Node

65nm/TSMC

Type

Hard IP

Maturity

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Overview

The S3TD300M12BT65GPA is a triple-DAC designed to be loaded by double terminated 75 Ohm Lines.The gain of the DAC is 6-bit controllable over a range
from -8dB to 0dB. This is achieved with integrated bias current circuitry.This block is also compatibly with CLN55GP shrink process.

Features

2.5V and 1.0V Supplies

6-bit Gain Control

Single-Ended or Differential Output Range

Full scale output currents 17mA to 34mA

DNL< ±1LSB Typ.; INL< ±3LSB Typ

Max Output Swing 1.3V Single-ended

Deliverables

Integration Support

Datasheet, Characterization Report

Flat Netlist (cdl), Abstract View (lef)

Layout View (gds2), Timing (lib)

Behavioral Model (Verilog)

Market Category

Consumer Electronics

Datasheet

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Size

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"S3 helped us to enter volume production rapidly by achieving first-time-right silicon resulting in a best-in-class performance product. The high level of integration achieved has made it possible to offer customers a low-cost bill of material solution that perfectly meets our customers' requirements. One of the key benefits of engaging with S3 was their ability to combine their silicon-proven IP and professional services to deliver complete solutions. "

Dirk Wieberneit, VP & General Manager of Product Development
Micronas

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