IPSEC L3 ESP/AH Protocol processing Engine with crypto engines (AES, TDES, RC4, SHA, MD5)

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Posedge Inc.

IP Name

PE-IPSEC-1.0 - IP Security Proctocol Processing En

Provider

Posedge Inc.

Description

IPSEC L3 ESP/AH Protocol processing Engine with crypto engines (AES, TDES, RC4, SHA, MD5)

Categories

IP Catalog : Digital Core IP : Security : Authentication

IP Catalog : Digital Core IP : Security : Content Inspection

IP Catalog : Digital Core IP : Security : Encryption

Portability

ASIC, FPGA, Structured

Process Node

all

Type

Soft IP

Maturity

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Overview

Posedge's IPSec is a complete IPSec protocol processor for IPV4 and IPV6. The IP is highly flexible with a programmable controller for ESP/AH encapsulation and the crypto engines are implemented in hardware. The high performance engine can process one gigabit of short IP packets per second (40 byte) at the packet level. Posedge's IPSec provides DMA type of interface for programming pointers to the security association data, packet pointers. The DMA perform
scatter/gather data fetching and security keys along with the keys. The soft processing engine in the IPSec processor performs the header (ESP/AH) insertion, padding on the fly, and presents the appropriate packet segments to the hardware engines. The hardware engines perform the encryption and authentication in sequence or in parallel depending on in-bound or out-bound traffic.

Features

• Scalable for GPON and GEPON architectures
• Highly scalable for multiple Ethernet ports or peripherals
• Fast path / slow path architecture
• Scalable architecture based on performance requirements
• Scalable packet classification with multiple coherent processors, DDR bandwidth, and local memory
• Multiple 32-bit RISC engines
• Complex functions like QOS and buffer management in Hardware
• DDR Queue Logic for optimal memory access
• Proprietary internal bus for optimal throughput and highest performance
• Separate busses for data transfer and packet communication control
• IEEE 802.3 compliant Gigabit Ethernet Mac core with support for jumbo frames, VLAN tagging, and flowcontrol
• Flexible I/O Interface with MII, RMII, and GMII interfaces
• Single DDR interface shared across different functions
• PHY Agnostic Architecture
• Hardware/software partitionin

Applications

• Small/Medium Business Enterprise access devices
• Residential Gateways
• Secure Wireless Handheld devices
• Remote Access Terminals
• Managed Switches

Benefits

Delivers high performance due to presence of:
• Wireless Access Points (WAP)
• Gateways
• GEPON/GPON residential
• SMB gateways
• CO-Aggregators for xDSL
• xPON

Features

Processes IPV4 / IPV6 packets

Performs ESP or AH protocol

Encryption/Authentication are run in parallel

Encryption Engines - AES, TDES, RC-4

Authentication Engines - SHA-1, SHA-2, MD-5

Designs runs up to 200 MHz in 90 nm.

Has AHB/AXI Interface

Independent block to perform complete IPSEC Processing.

Can be easily integrated into an existing data path

Packet interface and Key interface is programmable

Deliverables

Fully Synthesizable RTL

Testbenches and Testcases

ASIC Synthesis Scripts

FPGA Synthesis and P&R Scripts

Documentation

Market Category

Communications

Datasheet

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Bus Interface

AHB/AXI

Protocols

AMBA 4.0 AHB
AMBA 4.0 APB
AMBA 4.0 ASB
AMBA 4.0 ATB
AMBA 4.0 AXI
DSL
Ethernet

Gate Count

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QIP Rating

This IP is not yet QIP rated.

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