USB2.0 IP is a HS_FS USB controller, OTG capable, dual role usb2_0 compatible

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Innovative Logic

IP Name

MUSBMHDRC USB 2_0 MULTI-POINT DUAL-ROLE CONTROLLER

Provider

Innovative Logic

Description

USB2.0 IP is a HS_FS USB controller, OTG capable, dual role usb2_0 compatible

Categories

IP Catalog : Digital Core IP : Controllers : USB

IP Catalog : Digital Core IP : Controllers : USB

Portability

ASIC, FPGA

Process Node

all

Type

Soft IP

Maturity

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Overview

The MUSBMHDRC is a versatile design that provides in a single core:
- the function controller of a high-/full-speed USB peripheral;
- a 'Dual-role' USB controller for point-to-point 'On-The-Go' (OTG) communications with another USB function (which can be either high-speed, full-speed or low-speed); and
- (when connecteded to a hub) the host controller for a multi-point USB system.
in turn, allowing the device in which the MUSBMHDRC core is used to switch between these different roles as required.

The core complies both with the USB 2.0 standard for high-speed and full-speed functions and with the On-The-Go supplement to the USB 2.0 specification. The USB On-The-Go specification has been introduced to provide a low-cost connectivity solution for consumer portable devices such as mobile phones, PDAs, digital still cameras and MP3 players. Devices that are solely peripherals can initiate transfers through a Session Request Protocol (SRP) while Dual-role devices support both SRP and Host Negotiation Protocol (HNP) and can take on the role of either Host or Peripheral as required. The MUSBMHDRC can also carry out transaction translation, thereby allowing full- or low-speed devices to be used with a USB 2.0 hub. (Split transactions are also supported.

The MUSBMHDRC is user-configurable for up to 15 'Transmit' endpoints and/or up to 15 'Receive' endpoints in addition to Endpoint 0. (The use of these endpoints for IN transactions and OUT transactions depends on whether the MUSBMHDRC is being used as a peripheral or as a host. When used as a peripheral, IN transactions are processed through Tx endpoints and OUT transactions are processed through Rx endpoints. When used as a host, IN transactions are processed through Rx endpoints and OUT transactions are processed through Tx endpoints.) These additional endpoints can be individually configured in software to handle either Bulk transfers (which also allows them to handle Interrupt transfers), Isochronous transfers or Control transfers. Further, the endpoints can also be allocated to different target device functions on the fly – maximizing the number of devices that can be simultaneously supported.
Each endpoint requires a FIFO to be associated with it. The MUSBMHDRC has a RAM interface for connecting to a single block of synchronous single-port RAM which is used for all the endpoint FIFOs. (The RAM block itself needs to be added by the user)

The FIFO for Endpoint 0 is required to be 64 bytes deep and will buffer 1 packet. The RAM interface is configurable with regard to the other endpoint FIFOs which may be from 8 to 8192 bytes in size and can buffer either 1 or 2 packets. Separate FIFOs may be associated with each endpoint: alternatively a Tx endpoint and the Rx endpoint with the same Endpoint number can be configured to use the same FIFO, for example to reduce the size of RAM block needed, provided they can never be active at the same time.
The MUSBMHDRC is offered with a 32-bit synchronous CPU interface designed for connection to an AMBA AHB bus1. The interface supports use with an AHB bus running at a wide range of bus speeds. Multi-layer operations on the AHB bus are also supported. The MUSBMHDRC can also be readily connected to a range of other standard buses through the addition of a suitable wrapper/bridge.

There is also support for DMA access to the Endpoint FIFOs, including the option of a built-in DMA controller.

The MUSBMHDRC provides a UTMI+ Level 3-compatible interface for connecting to a suitable USB high/full-speed transceiver via an 8 bit transceiver interface. (The use of a Level 3 PHY allows low-speed devices to be used with a USB 1.1 hub.) An optional ULPI Link Wrapper is included for connecting to ULPI-compatible PHYs.

Features

Operates either as the function controller of a high- /full-speed USB peripheral or as the host/peripheral in point-to-point or multi-point communications with other USB functions

Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the On-The-Go supplement

Supports OTG communications with one or more high-, full- or low-speed device

Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP

Supports Suspend and Resume signaling

UTMI+ Level 3 Transceiver Macrocell Interface, with optional ULPI Link Wrapper

Configurable for up to 15 additional Transmit endpoints and up to 15 additional Receive endpoints and • Offers dynamic allocation of endpoints, to maximize number of devices supported

Configurable FIFOs, including the option of dynamic FIFO sizing

High-level 32-bit AMBA AHB-compatible CPU interface

Supports soft connect/disconnect

Deliverables

Both Verilog and VHDL RTL files

functional testbenches

synthesis scripts and scan test scripts

Documents

Market Category

Consumer Electronics

Datasheet

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Bus Interface

AHB

Gate Count

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QIP Rating

This IP is not yet QIP rated.

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