SSTL_18 Pad Set ( 90G)

Estimate your chip with this semiconductor IP

Aragio Solutions

IP Name

SSTL_18

Provider

Aragio Solutions

Description

SSTL_18 Pad Set ( 90G)

Categories

IP Catalog : Off-Chip Interface IP

IP Catalog : Off-Chip Interface IP : I/O Libraries : Specialty I/O

IP Catalog : Off-Chip Interface IP : I/O Libraries : General Purpose I/O

Portability

ASIC, FPGA, Structured

Process Node

90nm/GLOBALFOUNDRIES/G

Type

Hard IP

Maturity

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Overview

The SSTL_18 pad set is a full complement of I/O, power, and spacer cells that are necessary to assemble a padring by abutment. Since the SSTL_18 normally operates with its own isolated power domain (1.8V), a "rail-splitter" support cell (SPP_RS_005_18V) is included to allow the designer to easily break the lines that should not connect to the rest of the padring, while allowing VDD and VSS to be continuous within the padring. The output circuitry is designed with 2.5-volt FET's, but all parameters are guaranteed only at 1.8 volts (±10%). The cells are designed to provide the user with the option of either 60% or full drive that is fully compliant with the JEDEC standard JESD8-15a specification up to 400 MHz (DDR800) with balanced load management.

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Bus Interface

DDR Memory

Size

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QIP Rating

This IP is not yet QIP rated.

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