HDLC Protocol Controller Core

CAST

HDLC Protocol Controller Core

• IP Catalog : Digital Core IP : Controllers : Other

• # LAPB/LAPD controlling machine providing * modulo 8 frame numbering * modulo 128 frame numbering * one- or two-byte addressing * automatically generated responses
• # Serial Peripheral Interfaces * Bit stuffing * BOF and EOF flags generation * Support for RTS/CTS modem lines * Support for CD modem line * Collision detection in bus configuration
• Receive Length Check
• # Three modes of receive operation * auto mode (with address recognition and control field insertion) * non-auto mode (with address recognition) * transparent mode (without address recognition)
• # Receive and transmit blocks * Interrupt transfer mode * DMA transfer mode
• # Separate FIFO's * 64-bytes long receive FIFO * 64-bytes long transmit FIFO * 16-bytes long address FIFO for storing up to 16 small frames in the receive FIFO
• # Single or dual independent channel versions * Separate DMA lines for each channel * Common data bus and interrupt line
• # Single or dual independent channel versions * Separate DMA lines for each channel * Common data bus and interrupt line
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
• Configurability * Two top-level architectures allowing implementing single or double channel cores available.

• # HDL RTL source code (soft core) or a post-synthesis EDIF netlist (firm core) # An example single-channel design
• Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) that instantiates example design, test bench environmental design, external DP RAM, clock generator, and monitors that compare simulation results with expected results
• Simulation script, vectors, expected results, and comparison utility;
• Synthesis (soft) or place and route (firm) script
• Comprehensive user documentation, including detailed specifications and a system integration guide