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SuperSpeed USB3.0 PHY for TSMC65nm

SuperSpeed USB3.0 PHY for TSMC65nm

Overview:

The Cadence® SuperSpeed USB 3.0 IP is a fully integrated USB3.0 interface solution, optimized to reduce the cost of integrating and verifying a system-on-a-chip and the associated embedded software. The solution can contain either a host or device controller, configured to meet the exact functional and integration needs of the system. Related Integration-Optimized IP from Cadence 1) Superspeed USB3.0 Host Controller 2) Superspeed USB3.0 Device Controller

Deliverables

Verilog Model (.v), Abstract (.LEF),

LVS Netlist (.cdl), Timing model (.lib),

GDSII (with associated stream map file), Physical Verification Summary Files

CIP-1011

Features

Compliant with USB3.0 Specification Version 1.0

Spread spectrum clock/data recovery system and data scrambling to minimize EMI

8b/10b encode/decode

Low power: supports all USB 3.0 power management modes, and includes extensive low power features

USB3.0 PIPE interface with configurable width (8/16/32 bits)

Advanced mixed signal analog tools and techniques insure high yield and margin for package and board variations

Optional USB2.0 PHY, for backward compatibility, with UTMI/ULPI interfaces

Details

Category

Portability

Process Node

Type

Maturity

Market Category

Bus Interface

QIP Rating

IP Catalog : On-Chip Bus IP : USB

ASIC

65nm/TSMC/LP, G, GP

Hard IP

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Consumer Electronics Data Processing Others

PIPES

This IP is not yet QIP rated.

Vendor

The Cadence Incisive Verification IP Portfolio enables metric-driven verification, resulting in

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