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Cadence Design IP SuperSpeed USB3.0 PHY

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IP Name
SuperSpeed USB3.0 PHY for TSMC65nm
Provider

Cadence

Description

Cadence Design IP SuperSpeed USB3.0 PHY

Category
Portability
ASIC
Process Node
65nm/TSMC/LP, G, GP
Type
Hard IP
Maturity
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Overview
The Cadence® SuperSpeed USB 3.0 IP is a fully integrated USB3.0 interface solution, optimized to reduce the cost of integrating and verifying a system-on-a-chip and the associated embedded software. The solution can contain either a host or device controller, configured to meet the exact functional and integration needs of the system. Related Integration-Optimized IP from Cadence 1) Superspeed USB3.0 Host Controller 2) Superspeed USB3.0 Device Controller
Features
  • Compliant with USB3.0 Specification Version 1.0
  • Spread spectrum clock/data recovery system and data scrambling to minimize EMI
  • 8b/10b encode/decode
  • Low power: supports all USB 3.0 power management modes, and includes extensive low power features
  • USB3.0 PIPE interface with configurable width (8/16/32 bits)
  • Advanced mixed signal analog tools and techniques insure high yield and margin for package and board variations
  • Optional USB2.0 PHY, for backward compatibility, with UTMI/ULPI interfaces
Deliverables
  • Specification/Datasheet with Integration Guidelines,
  • Verilog Model (.v), Abstract (.LEF),
  • LVS Netlist (.cdl), Timing model (.lib),
  • GDSII (with associated stream map file), Physical Verification Summary Files
  • CIP-1011
Market Category
Consumer Electronics, Data Processing, Others
Datasheet
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Bus Interface
PIPES
Size
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QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"Cadence® USB 3.0 verification IP has enabled us to thoroughly verify that our designs comply with the USB 3.0 specification, and this new SSIC product demonstrates the company’s commitment to supporting engineers working with this key protocol. By supporting all popular verification methodologies and simulators, the Cadence VIP has enabled GUC to support our diverse customer base with high-quality SoC and IP verification coverage. "

James Cheng, Senior Vice President
Global Unichip

 
 
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Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
IBM
SilTerra
SMIC
TSMC
Tower
UMC
X-FAB
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Category
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Portability
ASIC FPGA Structured
IP Quality
QIP Rated

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