USB 2.0 Device

Estimate your chip with this semiconductor IP

ASICS World Services

IP Name

USB_DEV2

Provider

ASICS World Services

Description

USB 2.0 Device

Category

IP Catalog : On-Chip Bus IP : USB

Portability

ASIC, FPGA, Structured

Process Node

40nm

Type

Soft IP

Maturity

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Overview

A USB 2.0 Device IP Core that provides high performance small footprint solution for quick and easy implementation of a USB Device interface. The USB 2.0 Device IP Core is ideal for applications where the target device must act as a peripheral only. It provides portable devices with a cost-effective way of conducting point-to-point communications using the USB bus.

Features

Fully USB 2.0 Certified

USB 2.0 high performance operation

UTMI +L2 and ULPI PHY Interfaces

High Speed and Full Speed mode support

Up to 16 endpoints

Bulk, interrupt and isochronous transfers

WISHBONE, AHB, OPB, PLB and AVALON SoC Interface

No dedicated local memory required

Compact and cost-effective solution for SoC

Deliverables

Verilog source code or netlist

Test Bench (Verilog Source Code)

Documentation

Reference design incl. C code

Free Tech Support

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Bus Interface

WISHBONE, AHB, OPB, PLB, OCP and AVALON

Gate Count

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QIP Rating

This IP is not yet QIP rated.

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	USB-OTG2			USB 2.0 OTG (LS, FS and HS)
	USB_DEV2			USB 2.0 Device
	USB-OTG2-ULPI			USB 2.0 OTG (LS, FS and HS) with ULPI interface
	USB-OTG2-AHB			USB 2.0 OTG (LS, FS and HS) with AHB interface
	USB-OTG2-OCP			USB 2.0 OTG (LS, FS and HS) with OCP interface