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I2C Master and Slave

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ASICS World Services
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IP Name
I2C_MS1
Provider

ASICS World Services
Description

I2C Master and Slave
Category
Portability
ASIC, FPGA, Structured
Process Node
130nm
Type
Soft IP
Maturity
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Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously.
Deliverables
  • Verilog source code or netlist
  • Test Bench (Verilog Source Code)
  • Documentation
  • Free Tech Support
Market Category
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
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Bus Interface
WISHBONE, AHB, OPB, PLB, OCP and AVALON
Gate Count
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QIP Rating  This IP is not yet QIP rated.
 
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