The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divider in the internal feedback path, and a 1-16 divider at the output. The outputs are 50% duty cycle for all output divider values. It delivers optimal jitter performance over all multiplication settings and is suitable for system clock, DDR and general purpose applications where small size, low power and low cost are important.
- Designed as a wide range clock multiplier with deskew capability.
- Delivers optimal jitter performance over all multiplication settings.
- Low area and Low power.
- Suitable for system clock, DDR and general purpose applications.
- Ideal for cost sensitive applications.
- GDSII (100% DRC and LVS clean)
- LVS Spice netlist
- Verilog model
- Synopsys synthesis model
- LEF for clock generator PLL
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
"Our mission is to provide predictable, reliable and cost-effective ASIC solutions, while reducing risk at each step of the process and improving time-to-market. True Circuits PLLs and DLLs are feature rich, easily integrated and well supported, helping us to deliver quality analog IP and faster design implementations to our ASIC customers. "
Hans Bouwmeester, Director of IP Open-Silicon, Inc.