Sub-frame latency JPEG 2000 decoder

Estimate your chip with this semiconductor IP

Barco Silex

IP Name

BA129 Sub-frame latency JPEG 2000 decoder

Provider

Barco Silex

Description

Sub-frame latency JPEG 2000 decoder

Categories

IP Catalog : Digital Core IP : Audio/Video : Image Coders/Decoders : JPEG

IP Catalog : Digital Core IP : Audio/Video : Video Coders/Decoders

Portability

ASIC, FPGA

Process Node

all

Type

Soft IP

Maturity

Please login or register to view this data

Overview

Capitalizing on its long-term experience with JPEG 2000 hardware coding, Barco Silex offers a large JPEG 2000 portfolio including this compact, real-time hardware decoder engine that is optimized for low latency video applications.

The core architecture offers a flexible and high-speed solution to meet the challenges of high-end broadcast performance requirements, sustaining up to 180 frames per second in 1080i format, for compressed stream bitrates extending up to 400 megabit per second.

The BA129 core decodes streams that are compliant with the ISO/IEC 15444-1 specification (JPEG 2000) and supports single-tiled frames up to 1080p or larger. This IP is the complement of the BA130 low-latency JPEG 2000 encoder IP, to which it can be directly connected.

The core performs the complete video decompression operations of the normalized decoding process: stream parsing and header decoding, entropy decoding, inverse quantization and inverse discrete wavelet transform (IDWT). It accepts a JPEG 2000 file at its input interface and generates decoded samples at its output interface with up to 12 bits per color sample, an optional module generates the video output in real-time, without any buffering, to preserve the latency performances.

The BA129 IP provides a single-chip FPGA solution for 720p30-180, 1080i30-180 and 1080p30-90 video modes, with a total pixel-to-pixel latency below 10ms for 1080i/p60, below 5ms for 1080i/p120 and below 3ms for 1080i/p180 when used together with the BA130 encoder.

The flexible FPGA architecture allows the user to build a secure decoder by integrating Barco Silex cryptography IP cores.

Features

Sub-frame latency decoding (< 5ms)

Full image decoding (no tiling)

Compliant with JPEG 2000 (ISO/IEC 15444-1)

Integrated Intellectual Property (IP) core for JPEG 2000

Customizable input bit rate up to 200Mbps / 400Mbps

Single-chip FPGA solution

Fully autonomous decoder with automatic parameter extraction, minimal user intervention

Fully synchronous design

Deliverables

RTL code or netlist

Functional simulation testbench

Synthesis script

Full documentation

Market Category

Communications, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

Please login or register to view this data

Gate Count

Please login or register to view this data

QIP Rating

This IP is not yet QIP rated.

Related IP from Barco Silex you may be interested in...

	IP Name			Description
	BA115JPEGCD			Fast JPEG color decoder
	BA116JPEGCE			Fast JPEG color encoder
	BA110 HD/DCI JPEG 2000 Encoder			Multi-channel HD/DCI JPEG 2000 encoder
	BA109 HD/DCI JPEG 2000 Decoder			Multi-channel HD/DCI JPEG 2000 decoder
	BA130 Sub-frame latency JPEG 2000 encoder			Sub-frame latency JPEG 2000 encoder