ntRSC_IESS
ntRSC_IESS
Overview:

ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several programming features including codeword size, error threshold, number of parity bytes, reverse or forward order of the output, mode of operation (encode, decode or pass-through), shortened code support, erasures or error only decoding. Very low latency, high speed, simple interfacing and programmability make this core ideal for many applications including Intelsat IESS-308, DTV, DBS, ADSL, Satellite Communications, High performance modems and networks.

Deliverables

VHDL or Verilog test benches and example configuration files
C++ model
Comprehensive technical documentation
Technical support

Features

Polynomial compliant to Intelsat IESS-308; RTCA DO-217 AppendixF, Revision D Standard
High throughput rate
Fully programmable to correct from 1 to 10 error bytes or 20 erasure bytes per block
Configurable odd or even number of check bytes
Codeword lengths can be programmed from 3 to 255 bytes
Can be configured in encode, decode or pass-through mode of operation
Outputs corrected bytes or correction vectors in forward or reverse order
Supports continuous or burst data transfer and programmable error threshold to help in determining channel performance
Byte wide synchronous I/O ports with internal buffering and dedicated control pins enable non-continuous system data flow
Fully synchronous design, using single clock

Details

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