Open-Silicon's Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI. The Interlaken IP supports the following Interlaken Alliance specifications:
Designed and tested to be easily synthesizable into many ASIC technologies, Open-Silicon's Interlaken IP Core was uniquely built to work with off-the-shelf SerDes from leading technology vendors. Using vendor specific, proven, SerDes allows Open-Silicon customers to quickly integrate the Interlaken IP Core into the customer's technology of choice.
4-channel Interlaken-Look-Aside protocol
25 Gbps SerDes support
Up to 600Gbps high-bandwidth performance
Interlaken Retransmit Extension support
Support for 256 logical channels, plus 8 bit channel extension for up to 64K channels
Support for SerDes speeds from 3.125Gbps to 25Gbps