Interlaken Protocol IP

Estimate your chip with this semiconductor IP

Open-Silicon

IP Name

Open-Silicon Interlaken IP Core

Provider

Open-Silicon

Description

Interlaken Protocol IP

Categories

IP Catalog : Digital Core IP : Communications : Wired : Cell/Packet

IP Catalog : Digital Core IP : Communications : Wired : Other

IP Catalog : Digital Core IP : Controllers : Other

Portability

ASIC

Process Node

all

Type

Soft IP

Maturity

Please login or register to view this data

Overview

Open-Silicon's Interlaken IP is a scalable, high-speed chip-to-chip interface protocol that builds on the channelization and per-channel flow control features of SPI4.2, while reducing the number of chip I/O pins by using high-speed SerDes technology, similar to XAUI. The Interlaken IP supports the following Interlaken Alliance specifications:

- Interlaken Protocol Definition, v1.2
- Interlaken Look-Aside Protocol Definition, v1.1
- Interlaken Interop Recommendations, v1.6
- Interlaken Retransmit Extension, v1.1

Designed and tested to be easily synthesizable into many ASIC technologies, Open-Silicon's Interlaken IP Core was uniquely built to work with off-the-shelf SerDes from leading technology vendors. Using vendor specific, proven, SerDes allows Open-Silicon customers to quickly integrate the Interlaken IP Core into the customer's technology of choice.

Features

4-channel Interlaken-Look-Aside protocol

25 Gbps SerDes support

Up to 600Gbps high-bandwidth performance

Interlaken Retransmit Extension support

Support for 256 logical channels, plus 8 bit channel extension for up to 64K channels

Support for SerDes speeds from 3.125Gbps to 25Gbps

Configurable number of lanes from 1 to 48

Simultaneous In-band and Out-of-Band flow control

Programmable calendar

Fully-programmable SerDes lane mapping

Market Category

Communications

Datasheet

Please login or register to view this data

Gate Count

Please login or register to view this data

QIP Rating

This IP is not yet QIP rated.

Related IP from Open-Silicon you may be interested in...

	IP Name			Description
	100G MAC			100G Ethernet Media Access Controller
	40G MAC			40G Ethernet Media Access Controller IP
	40G PCS			40G Physical Coding Sublayer IP
	100G PCS			100G Physical Coding Sublayer IP
	BCH Error Correction and Detection			BCH ECC is a complete BCH encoder and decoder IP that is implemented over GF2(13).