Multiply Adder
Multiply Adder
Overview:

The Multiply Adder IP performs a multiplication of two operands and adds (or subtracts) the full-preciison product to a third operand.The Multiply Adder IP is implemented using Xtreme DSP™ slices and operates on signed or unsigned data.

Features

Supports multiplier inputs ranging from 1 to 52 bits unsigned or 2 to 53 bits signed and an add or subtract operand input ranging from 1 to 105 bits unsigned or 2 to 106 bits signed
Optional pipelined operation
For use with Xilinx CORE Generator™ and Xilinx AccelDSP™ Synthesis Tool

Details

Category

Portability

Process Node

Type

Maturity

Market Category

QIP Rating

IP Catalog : Digital Core IP : DSP : Other

FPGA

Soft IP

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Automotive Communications Consumer Electronics Data Processing Industrial and Medical Military/Civil Aerospace Others

This IP is not yet QIP rated.

Vendor

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