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MIPI HSI Verification IP in native SystemVerilog (UVM/OVM/VMM) & Verilog

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IP Name
MIPI_HSI_nVS
Provider

nSys Design Systems
Description

MIPI HSI Verification IP in native SystemVerilog (UVM/OVM/VMM) & Verilog
Type
Verification IP
Protocols
MIPI M-PHY
Design Category
Bus: On Chip
Maturity Status
Available on Request
Overview
The MIPI HSI nVS is a comprehensive Verification IP solution for pre-silicon functional verification of MIPI HSI (High-speed Synchronous Serial Interface) compliant designs. The nVS allows design and verification engineers to test the entire functionality of their MIPI compliant designs quickly and extensively.

Availability of Test Suites enables the designers to focus on features unique to their design. The nVS leverages advanced verification techniques in creating a versatile testbench environment.
Features
  • Compliant to MIPI HSI Physical Layer Version 1.01.00 / 1.0
  • Supports all control channel commands (32-bit)
  • Supports extensive error-insertion & error-detection capabilities
  • Programmable Bus-Monitor for debugging of complex test scenario
  • On-the-fly protocol and data checking/scoreboard
  • Supports programmable number of channels for data transfer
  • Supports programmable PDU lengths from 0 to 256 K
  • User-configurable timeout for power-on procedure
  • Works on a recovered clock based on DATA and FLAG signals
  • Generates detailed Assertion coverage report
Deliverables
  • Validated MIPI HSI Verification Suite: BFM/Agent, Bus-Monitor
  • Test Suites in source code
  • User Manual & Application notes
Market Category
Consumer Electronics
Datasheet
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QIP Rating  This IP is not yet QIP rated.
 
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