MIPI HSI Verification IP in native SystemVerilog (UVM/OVM/VMM) & Verilog
Bus: On Chip
Available on Request
The MIPI HSI nVS is a comprehensive Verification IP solution for pre-silicon functional verification of MIPI HSI (High-speed Synchronous Serial Interface) compliant designs. The nVS allows design and verification engineers to test the entire functionality of their MIPI compliant designs quickly and extensively.
Availability of Test Suites enables the designers to focus on features unique to their design. The nVS leverages advanced verification techniques in creating a versatile testbench environment.
Compliant to MIPI HSI Physical Layer Version 1.01.00 / 1.0