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MIPI_HSI_nVS

nSys Design Systems

MIPI_HSI_nVS

Overview:

The MIPI HSI nVS is a comprehensive Verification IP solution for pre-silicon functional verification of MIPI HSI (High-speed Synchronous Serial Interface) compliant designs. The nVS allows design and verification engineers to test the entire functionality of their MIPI compliant designs quickly and extensively.

Availability of Test Suites enables the designers to focus on features unique to their design. The nVS leverages advanced verification techniques in creating a versatile testbench environment.

Deliverables

Test Suites in source code

User Manual & Application notes

Features

Compliant to MIPI HSI Physical Layer Version 1.01.00 / 1.0

Supports all control channel commands (32-bit)

Supports extensive error-insertion & error-detection capabilities

Programmable Bus-Monitor for debugging of complex test scenario

On-the-fly protocol and data checking/scoreboard

Supports programmable number of channels for data transfer

Supports programmable PDU lengths from 0 to 256 K

User-configurable timeout for power-on procedure

Works on a recovered clock based on DATA and FLAG signals

Generates detailed Assertion coverage report

Details

Category

Portability

Process Node

Type

Maturity

Market Category

Protocols

QIP Rating

Verification IP

Consumer Electronics

MIPI M-PHY

This IP is not yet QIP rated.

Vendor

nSys offers the world's largest portfolio of Verification IPs and also leverages them to provid

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