AMBA 2.0 APB Master

Estimate your chip with this semiconductor IP

Synopsys

IP Name

VIP, AMBA 2.0, APB Master

Provider

Synopsys

Description

AMBA 2.0 APB Master

Type

Verification IP

Protocols

AMBA 2.0 APB

Design Category

Bus: On Chip

Maturity Status

Available on Request

Overview

The Verification IP (VIP) for the AMBA® interface provides a quick and efficient way to verify AMBA SoC designs by implementing advanced techniques for more productive verification. The VIP for AMBA includes the following components: Master, Slave, Monitor, and Interconnect for AMBA 3 AXI, and AMBA 2.0 AHB/APB. The VIP for AMBA 3 AXI has achieved the "AMBA 3 Assured" certification logo. This logo indicates that the DesignWare® VIP has been proven to correctly implement the AMBA 3 AXI specification, as defined by the assertion-based AXI protocol rule sets available from ARM®. The VIP for AMBA supports the SystemVerilog design language and the Verification Methodology Manual (VMM). The VMM defines a coverage driven methodology for SystemVerilog using a constrained random environment. The Master and Slave VIP can be configured to represent any AMBA-based master or slave component. The protocol monitors provide debug information, protocol violation notification and protocol coverage metrics. In addition the monitor includes performance monitoring capabilities enabling designers to accurately measure the bandwidth and latency of the subsystem.

Features

Compliant with the latest AMBA 3 AXI and AMBA 2.0 specification

Supports all AMBA 3 AXI and AMBA 2.0 data and address widths

AMBA 2.0 VIP Supports AMBA, AMBA-Lite and multi-layer AHB

Supports all protocol transfer types and response types

Supports constrained randomization of protocol attributes

Checks for all protocol violations

Logs transactions and reports on protocol violations and coverage

Includes user-configurable message formatting

Leverages Synopsys Discovery™ Verification Platform technology with full support for SystemVerilog, Vera®, Verilog and VHDL verification environments

Includes protocol-based scenario generation

Market Category

Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "

Laurent Sibony, Director of ASIC Designs
Sequans

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