Synopsys DesignWare® AMBA® Advanced eXtensible Interface (AXI) Verification IP (VIP) provides a quick and efficient way to verify AMBA AXI-based SoC designs by bringing advanced techniques for more productive verification. AMBA AXI technology enhances the existing AMBA specification providing a protocol that has been designed to meet the needs of ultra-high-performance and complex system-on-chip (SoC) designs. Supporting register-sliced signaling and out-of-order burst transactions, the AMBA AXI interface technology significantly improves intra-chip data transfers. The DesignWare AMBA AXI VIP includes the following components: AXI Master, AXI Slave, AXI Monitor, AXI Interconnect and a SystemClock Controller.
Compliant with the latest AMBA 3 AXI and AMBA 2.0 specification
Supports all AMBA 3 AXI and AMBA 2.0 data and address widths
AMBA 2.0 VIP Supports AMBA, AMBA-Lite and multi-layer AHB
Supports all protocol transfer types and response types
Supports constrained randomization of protocol attributes
Checks for all protocol violations
Logs transactions and reports on protocol violations and coverage
Includes user-configurable message formatting
Leverages Synopsys Discovery™ Verification Platform technology with full support for SystemVerilog, Vera®, Verilog and VHDL verification environments
Includes protocol-based scenario generation
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "