PCI / PCI-X Master

Estimate your chip with this semiconductor IP

Synopsys

IP Name

VIP, PCI, X-Master

Provider

Synopsys

Description

PCI / PCI-X Master

Type

Verification IP

Protocols

PCI

Design Category

Bus: On Chip

Maturity Status

Available on Request

Overview

The PCI/PCI-X Verificatgion IP allows designers to test their design for proper operation and compliance to the PCI Local Bus specification or PCI-X Addendum. The model can be used to quickly create a virtual PCI or PCI-X system around a design. The PCI/PCI-X Verification IP features a complete set of high commands and enables extensive testing to ensure that your design is compliant to the latest PCI and PCI-X specification. The verification IP includes a bus Master, a bus Slave and a monitor that can be controled from Verilog, VHDL, Vera® or C in all major simulators. The Verification IP is available to all DesignWare® or DesignWare Verification Library licensees.

Features

Supports PCI 2.3 and PCI-X 2.0

Controllable from Verilog, VHDL, Vera

PCI-X 2.0 ECC, DDR, and QDR.

All Read/Write transactions

Split transactions

Error generation (bad data, address parity)

64-bit extension

64-bit addressing

User specified limit on number of retries the pcimaster_fx performs

User specified limit on timeout clocks

Market Category

Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "

Laurent Sibony, Director of ASIC Designs
Sequans

View More Testimonials

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