The PCI/PCI-X Verificatgion IP allows designers to test their design for proper operation and compliance to the PCI Local Bus specification or PCI-X Addendum. The model can be used to quickly create a virtual PCI or PCI-X system around a design. The PCI/PCI-X Verification IP features a complete set of high commands and enables extensive testing to ensure that your design is compliant to the latest PCI and PCI-X specification. The verification IP includes a bus Master, a bus Slave and a monitor that can be controled from Verilog, VHDL, Vera® or C in all major simulators. The Verification IP is available to all DesignWare® or DesignWare Verification Library licensees.
Supports PCI 2.3 and PCI-X 2.0
Controllable from Verilog, VHDL, Vera or C
Emulates the protocol of a PCI or PCI-X bus slave device at the pin and bus-cycle levels and performs timing violation checks
PCI-X 2.0 ECC, DDR, and QDR
Address and data stepping
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
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