USB 1.1, 2.0 and On-the-Go Host

Estimate your chip with this semiconductor IP

Synopsys

IP Name

VIP, USB 1.1, OTG Host

Provider

Synopsys

Description

USB 1.1, 2.0 and On-the-Go Host

Type

Verification IP

Protocols

USB2.0

Design Category

Bus: On Chip

Maturity Status

Available on Request

Overview

The DesignWare® USB On-The-Go (OTG) Verification IP provides a quick and efficient way to verify USB-based SoC designs for USB 1.1, USB 2.0, USB OTG, USB Transceiver MacroCell Interface (UTMI) or USB OTG Transceiver MacroCell Interface Plus (UTMI+). USB OTG offers the flexibility of configuring the model as a host or a dual role device. The model can be operated at high-speed (480Mbits/sec), full-speed (12Mbits/sec), or low-speed (1.5Mbits/sec) data transfer rates. The powerful bus functional capability generates transactions from simple high-level commands embedded in the testbench. As users quickly develop tests that generate and respond to bus activity, they can depend on the USB monitor to verify bus compliance of the DUT. When used as a device, the model can be configured as a standard USB 2.0 device or as a USB OTG device with support for Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) compliance checking. This model, when combined with DesignWare® USB On-The-Go Core IP, provides a complete USB-based subsystem solution. The Verification IP is available in the DesignWare Library and DesignWare Verification Library.

Features

Compliant with: USB 1.1, USB 2.0, USB OTG

Supports UTMI and UTMI+ specification

NTB, RVM, VMM and functional coverage support

TesSystemVerilog, Vera®, Verilog, VHDL, and CSRP and HNP compliance checkingtbench neutral

Operates at high, full or low speed

Protocol checking and transaction logging

Programmable monitor interrupts

Programmable error injection and detection

Includes protocol-based scenario generation

Market Category

Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "

Laurent Sibony, Director of ASIC Designs
Sequans

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